VHDL

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The Spade Hardware Description Language https://hackaday.com/2025/04/13/the-spade-hardware-description-language/ #HardwareDescriptionLanguage #SpadeLanguage #hardware #verilog #FPGA #ASIC #fpga #vhdl #hdl

The Spade Hardware Description Language - Spade is an open-source hardware description language (HDL) developed at Linköping... - https://hackaday.com/2025/04/13/the-spade-hardware-description-language/ #hardwaredescriptionlanguage #spadelanguage #hardware #verilog #fpga #asic #vhdl #hdl

GNU/ #emacs as a full fledged #vhdl #ide, using #guix.

https://git.sr.ht/~csantosb/emacs.vhdl-ide

Might as well give this a shot.

I want to get out of my current field and do something I can be happy with for a company I can feel good about. I'm currently in the SE US, but want to move back to mid-Atlantic/ North East. Remote is good too.

I have over 10 years of experience of various odd jobs in the embedded electronics space. I'm often moved around as I pick things up quickly and give insight others find valuable.
I've done FPGA verification, FPGA design, software and hardware reverse engineering. I have at least some experience with most standard embedded communication protocols and am very at home in electronics labs. I've recently been self teaching web dev using #Flask. I know #VHDL , #python , a bit rusty on #tcl , #c , and #cpp.
#FediHire #getfedihired

#cocotb, a #freesoftware cosimulation testbench environment for verifying #VHDL and #SystemVerilog #RTL using #Python, is part now of #guixscience channel. It may be used as any other #guix package with a simple

guix install python-cocotb

This means too that pre-built substitutes are available online .

#modernhw

In the mood for the littlest bit of #FPGA #GameDev? Check out this pico-ice based #pong demo. Just need #VGA #pmod and #UART connected to host PC. #HDL #hardware #RTL #Verilog #VHDL #HLS #lattice #ice40 https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/pong_top.c

Gifted a new #FPGA dev board this season? PipelineC aims to make #hardware description easier for #embedded folks.
Check out the new getting start page. Happy to help you get going! #hdl #verilog #vhdl #hls #HLS
https://github.com/JulianKemmerer/PipelineC/wiki/Dev-Board-Setup

Gotta love that moment when your #VHDL project works first try on real hardware.

Did You Know YoSys Knows VHDL Too? https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/ #verilog #yosys #FPGA #fpga #vhdl

Did You Know YoSys Knows VHDL Too? - We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while... - https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/ #verilog #yosys #fpga #vhdl

This #VHDL code is producing low outputs when I'm expecting high. Guess I'll just invert the signal instead of looking into the actual problem. Surely this won't cause problems later and result in 2 hours of debugging. Surely not...

Have been super pleased with the #ice40 #FPGA and #raspberrypi board that https://pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice #HDL #Verilog #VHDL #hardware #embedded

#ghdl (in its #clang variant), a #freesofware #vhdl analyzer, compiler, simulator and synthesizer, is part now of #guixscience channel. It may be used as any other #guix package with a simple

guix install ghdl-clang

This means too that pre-built substitutes are available online.

#modernhw

I write my #VHDL code like I write my #Rust code, and nobody can stop me.

(Rust really teaches you some good habits that you can apply to every language I feel like...)

#ci testing of a #vhdl project in the #sourcehut build farm.

It runs a #ghdl simulation using the #osvvm verification library, creating a #guix local profile from a manifest file to handle all dependencies. Requirements are pulled from a custom repository. All #reproductible thanks to pinned guix channels.

https://builds.sr.ht/~csantosb/job/1363181

#modernhw

Calling all #HDL hackers! I need help in putting the #MIT #CADR onto a FPGA board. #VHDL, #Verilog, does not matter much. Who is up for a fun challange? #LispMachine

#Guix channel for #digitalelectronics design, mainly #vhdl and #fpga

https://gitlab.com/csantosb/guix/channel-electronics

So far, with #cocotb, #vunit, #yosys, #osvvm and #ghdl (including its yosys plugin).

Use with:

git clone --depth=1 https://git.sr.ht/~csantosb/guix.channel-electronics
guix install -L ./guix.channel-electronics ghdl-clang

#modernhw